Processor Architecture Lab
A comprehensive academic resource exploring computer organization, logic design, and processor architecture through rigorous experimentation and analysis.
Laboratory Experiments
Introduction to Processor Architecture
Introduction to processor architecture concepts, computer organization fundamentals, and basic computing principles.
View CodeBooth's Multiplication Algorithm
Implementation of Booth's Multiplication Algorithm for signed binary numbers using two's complement arithmetic.
View CodeRestoring Division Algorithm
Implementation of Restoring Division Algorithm to perform binary division of unsigned integers.
View CodeRipple Carry Adder Design
Design of Half Adder, Full Adder and 4-bit Ripple Carry Adder using Logisim digital circuit simulator.
View CodeALU Design
Design and simulation of an Arithmetic Logic Unit (ALU) capable of performing arithmetic and bitwise operations.
View CodeShift Register Design
Design of Serial-In Serial-Out (SISO), PIPO, Left Shift and Right Shift registers using Flip-Flops.
View CodeRAM and ROM Simulation
Simulation of RAM (Random Access Memory) and ROM (Read Only Memory) using Logisim digital circuit simulator.
View CodeCase Study: ISA, PCI and USB
Case study on different bus architectures including ISA, PCI and USB standards in computer systems.
View CodeCase Study: Multi-Core Processors
Case study on Multi-Core Processors, parallel processing architectures and performance optimization techniques.
View CodeTypes of Interrupts & Handling
Study of types of Interrupts (hardware, software, maskable) and techniques to handle interrupts in processors.
View CodeThe Wall
Collaborative
Study Notes
Amey Thakur
Author & Curator
Mega Satish
Author & Collaborator
Arithmetic Logic Visualizer
Booth's Algorithm Visualizer
An interactive visualizer for Booth's Multiplication Algorithm. Enter two signed integers to see the step-by-step bitwise operations, shifting, and accumulation processing used in modern processors.